Matthias Diener

Research
CV
Publications

Publications

Google Scholar profile

Journals

  1. Eduardo H. M. Cruz, João M. Maciel, Camila Clozato, Matheus S. Serpa, Philippe O. A. Navaux, Esteban Meneses, Mariela Abdalah, Matthias Diener. “Simulation-based evaluation of school reopening strategies during COVID-19: A case study of São Paulo, Brazil.” Epidemiology & Infection, 2021. [doi]

  2. Eduardo H. M. Cruz, João M. Maciel, Camila Clozato, Matheus S. Serpa, Philippe O. A. Navaux, Esteban Meneses, Mariela Abdalah, Matthias Diener. “The impact of school reopening strategies during COVID-19: A case study of Sao Paulo, Brazil.” arXiv, 2020. [url]

  3. Eduardo H. M. Cruz, Matthias Diener, Laércio L. Pilla, Philippe O. A. Navaux. “Online Thread and Data Mapping Using a Sharing-Aware Memory Management Unit.” ACM Transactions on Modeling and Performance Evaluation of Computing Systems (TOMPECS), 2020. [doi]

  4. Matthias Diener, Laxmikant V. Kale, Daniel J. Bodony. “Heterogeneous Computing with OpenMP and Hydra.” Concurrency and Computation: Practice and Experience (CCPE), 2020. [doi]

  5. Eduardo H. M. Cruz, Matthias Diener, Laércio L. Pilla, Philippe O. A. Navaux. “EagerMap: A Task Mapping Algorithm to Improve Communication and Load Balancing in Clusters of Multicore Systems.” ACM Transactions on Parallel Computing (TOPC), 2019. [doi]

  6. Matheus S. Serpa, Eduardo H. M. Cruz, Matthias Diener, Arthur M. Krause, Philippe O. A. Navaux, Jairo Panetta, Albert Farrés, Claudia Rosas, Mauricio Hanzich. “Optimization Strategies for Geophysics Models on Manycore Systems.” International Journal of High Performance Computing Applications (IJHPCA), 2019. [doi]

  7. Matthias Diener, Eduardo H. M. Cruz, Marco A. Z. Alves, Philippe O. A. Navaux, Israel Koren. “Affinity-Based Thread and Data Mapping in Shared Memory Systems.” ACM Computing Surveys (CSUR), 2016. [doi]

  8. Eduardo H. M. Cruz, Matthias Diener, Laércio L. Pilla, Philippe O. A. Navaux. “Hardware-Assisted Thread and Data Mapping in Hierarchical Multi-Core Architectures.” ACM Transactions on Architecture and Code Optimization (TACO), 2016. [doi]

  9. Matthias Diener, Eduardo H. M. Cruz, Philippe O. A. Navaux. “Modeling Memory Access Behavior for Data Mapping.” International Journal of High Performance Computing Applications (IJHPCA), 2016. [doi]

  10. Francis B. Moreira, Marco A. Z. Alves, Matthias Diener, Philippe O. A. Navaux, Israel Koren. “A Dynamic Block-Level Execution Profiler.”, Parallel Computing (PARCO), 2016. [doi]

  11. Matthias Diener, Eduardo H. M. Cruz, Marco A. Z. Alves, Philippe O. A. Navaux, Anselm Busse, Hans-Ulrich Heiss. “Kernel-Based Thread and Data Mapping for Improved Memory Affinity.” IEEE Transactions on Parallel and Distributed Systems (TPDS), 2015. [doi]

  12. Eduardo H. M. Cruz, Matthias Diener, Marco A. Z. Alves, Laércio L. Pilla, Philippe O. A. Navaux. “LAPT: A Locality-Aware Page Table for Thread and Data Mapping.” Parallel Computing (PARCO), 2015. [doi]

  13. Matthias Diener, Eduardo H. M. Cruz, Laércio L. Pilla, Fabrice Dupros, Philippe O. A. Navaux. “Characterizing Communication and Page Usage of Parallel Applications for Thread and Data Mapping.” Performance Evaluation, 2015. [doi]

  14. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux. “Communication-Aware Thread Mapping Using the Translation Lookaside Buffer.” Concurrency and Computation: Practice and Experience, 2015. [doi]

  15. Matthias Diener, Eduardo H. M. Cruz, Philippe O. A. Navaux, Anselm Busse, Hans-Ulrich Heiß. “Communication-Aware Process and Thread Mapping Using Online Communication Detection.”, Parallel Computing (PARCO), 2015. [doi]

  16. Eduardo H. M. Cruz, Matthias Diener, Marco A. Z. Alves, Philippe O. A. Navaux. “Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols.” Journal of Parallel and Distributed Computing (JPDC), 2014. [doi]

Conferences

  1. Douglas Pereira Pasqualin, Matthias Diener, André Rauber Du Bois, Mauricio Lima Pilla. “Sharing-Aware Data Mapping in Software Transactional Memory.” International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2021.

  2. Douglas Pereira Pasqualin, Matthias Diener, André Rauber Du Bois, Mauricio Lima Pilla. “Characterizing the Sharing Behavior of Applications using Software Transactional Memory.” International Symposium on Benchmarking, Measuring and Optimizing (Bench), 2020. Award for Best Paper. Award for Excellence for Reproducible Research. [doi]

  3. Douglas Pereira Pasqualin, Matthias Diener, André Rauber Du Bois, Mauricio Lima Pilla. “Online Sharing-Aware Thread Mapping in Software Transactional Memory.” International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2020. [doi]

  4. Douglas Pereira Pasqualin, Matthias Diener, André Rauber Du Bois, Mauricio Lima Pilla. “Thread Affinity in Software Transactional Memory.” International Symposium on Parallel and Distributed Computing (ISPDC), 2020. [doi]

  5. Eduardo Roloff, Matthias Diener, Luciano P. Gaspary, Philippe O. A. Navaux. “Exploring Instance Heterogeneity in Public Cloud Providers for HPC Applications.” International Conference on Cloud Computing and Services Science (CLOSER), 2019. [doi]

  6. Emmanuell D. Carreno, Marco A. Z. Alves, Matthias Diener, Eduardo Roloff, Philippe A. O. Navaux. “Multi-phased Task Placement of HPC Applications in the Cloud.” International Symposium on Parallel and Distributed Computing (ISPDC), 2019. [doi]

  7. Edson Luiz Padoin, Matthias Diener, Philippe O. A. Navaux, Jean-François Méhaut. “Managing Power Demand and Load Imbalance to Save Energy on Systems with Heterogeneous CPU Speeds.” International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2019. [doi]

  8. Matheus S. Serpa, Eduardo H. M. Cruz, Francis B. Moreira, Matthias Diener, Philippe O. A. Navaux, Dalvan Griebler, Luiz G. Fernandes. “Memory Performance and Bottlenecks in Multicore and GPU Architectures.” International Conference on Parallel, Distributed and Network-based Processing (PDP), 2019. [doi]

  9. Matthias Diener, Daniel J. Bodony, Laxmikant Kale. “Accelerating scientific applications on heterogeneous systems with HybridOMP.” International Meeting on High Performance Computing for Computational Science (VECPAR), 2018. [doi]

  10. Eduardo H. M. Cruz, Matthias Diener, Matheus Da Silva Serpa, Philippe O. A. Navaux, Laércio L. Pilla, Israel Koren. “Improving Communication and Load Balancing with Thread Mapping in Manycore Systems.” International Conference on Parallel, Distributed and Network-based Processing (PDP), 2018. [doi]

  11. Seonmyeong Bak, Harshitha Menon, Sam White, Matthias Diener, Laxmikant Kale. “Multi-level Load Balancing with an Integrated Runtime Approach.” International Symposium on Cluster, Cloud and Grid Computing (CCGrid), 2018. [doi]

  12. Eduardo Roloff, Matthias Diener, Luciano P. Gaspary, Philippe O. A. Navaux. “Exploiting Load Imbalance Patterns for Heterogeneous Cloud Computing Platforms.” International Conference on Cloud Computing and Services Science (CLOSER), 2018. [doi]

  13. Matthias Diener, Sam White, Laxmikant V. Kale, Michael T. Campbell, Daniel J. Bodony, Jonathan B. Freund. “Improving the memory access locality of hybrid MPI applications.” EuroMPI, 2017. [doi]

  14. Eduardo Roloff, Matthias Diener, Emmanuell D. Carreño, Luciano P. Gaspary, Philippe O. A. Navaux. “Leveraging cloud heterogeneity for cost-efficient execution of parallel applications.” International European Conference on Parallel and Distributed Computing (Euro-Par), 2017. [doi]

  15. Matthias Diener, Eduardo H. M. Cruz, Marco A. Z. Alves, Edson Borin, Philippe O. A. Navaux. “Optimizing memory affinity with a hybrid compiler/OS approach.” ACM International Conference on Computing Frontiers (CF), 2017. [doi]

  16. Francis B. Moreira, Matthias Diener, Philippe O. A. Navaux, Israel Koren. “Data mining the memory access stream to detect anomalous application behavior.” ACM International Conference on Computing Frontiers (CF), 2017. [doi]

  17. Eduardo Roloff, Matthias Diener, Luciano Paschoal Gaspary, Philippe O. A. Navaux. “HPC Application Performance and Cost Efficiency in the Cloud.” International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2017. [doi]

  18. Eduardo H. M. Cruz, Matthias Diener, Laércio L. Pilla, Philippe O. A. Navaux. “A Sharing-Aware Memory Management Unit for Online Mapping in Multi-Core Architectures.” International European Conference on Parallel and Distributed Computing (Euro-Par), 2016. [doi]

  19. Emmanuell D. Carreño, Matthias Diener, Eduardo H. M. Cruz, Philippe O. A. Navaux. “Automatic Communication Optimization of Parallel Applications in Public Clouds.” International Symposium on Cluster, Cloud and Grid Computing (CCGrid), 2016. [doi]

  20. Marco A. Z. Alves, Matthias Diener, Paulo Santos, Luigi Carro. “Large Vector Extensions inside the HMC.” Design, Automation and Test in Europe (DATE), 2016. [doi]

  21. Eduardo Roloff, Emmanuell Diaz Carreño, Jimmy K. M. Valverde-Sánchez, Matthias Diener et al. “Performance Evaluation of Multiple Cloud Data Centers Allocations for HPC.” Communications in Computer and Information Science, 2016. [doi]

  22. Matthias Diener, Eduardo Cruz, Marco A. Z. Alves, Philippe O. A. Navaux. “Communication in Shared Memory: Concepts, Definitions, and Efficient Detection.” International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2016. [doi]

  23. Artur Mariano, Matthias Diener, Christian Bischof, Philippe O. A. Navaux. “Analyzing and Improving Memory Access Patterns of Large Irregular Applications on NUMA Machines.” International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2016. [doi]

  24. Paulo Cesar Santos, Marco A. Z. Alves, Matthias Diener, Luigi Carro, Philippe O. A. Navaux. “Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency.” International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2016. [doi]

  25. Marco A. Z. Alves, Paulo C. Santos, Francis B. Moreira, Matthias Diener, Luigi Carro. “Saving Memory Movements Through Vector Processing in the DRAM.” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2015. [doi]

  26. Marco A. Z. Alves, Paulo C. Santos, Matthias Diener, Luigi Carro. “Opportunities and Challenges of Performing Vector Operations inside the DRAM.” International Symposium on Memory Systems (MEMSYS), 2015. [doi]

  27. Matthias Diener, Eduardo H. M. Cruz, Marco A. Z. Alves, Mohammad S. Alhakeem, Philippe O. A. Navaux, Hans-Ulrich Heiß. “Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems.” International European Conference on Parallel and Distributed Computing (Euro-Par), 2015. [doi]

  28. Marco A. Z. Alves, Carlos Villavieja, Matthias Diener, Francis B. Moreira, Philippe O. A. Navaux. “SiNUCA: A Validated Micro-Architecture Simulator.” International Conference on High Performance Computing and Communications (HPCC), 2015. [doi]

  29. Marco A. Z. Alves, Paulo C. Santos, Matthias Diener, Luigi Carro. “Reconfigurable Vector Extensions inside the DRAM.” International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015. [doi]

  30. Anselm Busse, Jan Schönherr, Matthias Diener, Philippe O. A. Navaux, Hans-Ulrich Heiß, “Partial Coscheduling of Virtual Machines Based on Memory Access Patterns.” ACM Symposium on Applied Computing (SAC), 2015. [doi]

  31. Matthias Diener, Eduardo H. M. Cruz, Philippe O. A. Navaux. “Locality vs. Balance: Exploring Data Mapping Policies on NUMA Systems.” International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2015. [doi]

  32. Eduardo H. M. Cruz, Matthias Diener, Laércio L. Pilla, Philippe O. A. Navaux. “An Efficient Algorithm for Communication-Based Task Mapping.” International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2015. [doi] Award for Best Paper.

  33. Eduardo H. M. Cruz, Matthias Diener, Marco A. Z. Alves, Laércio L. Pilla, Philippe O. A. Navaux. “Optimizing Memory Locality Using a Locality-Aware Page Table.” International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2014. [doi]

  34. Francis B. Moreira, Marco A. Z. Alves, Matthias Diener, Philippe O. A. Navaux, Israel Koren. “Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level.” International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2014. [doi]

  35. Matthias Diener, Eduardo H. M. Cruz, Philippe O. A. Navaux, Anselm Busse, Hans-Ulrich Heiß. “kMAF: Automatic Kernel-Level Management of Thread and Data Affinity.” International Conference on Parallel Architectures and Compilation Techniques (PACT), 2014. [doi]

  36. Marco A. Z. Alves, Carlos Villavieja, Matthias Diener, Philippe O. A. Navaux. “Energy Efficient Last Level Caches via Last Read/Write Prediction.” International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2013. [doi]

  37. Matthias Diener, Eduardo H. M. Cruz, Philippe O. A. Navaux. “Communication-Based Mapping using Shared Pages.” International Parallel & Distributed Processing Symposium (IPDPS), 2013. [doi]

  38. Anselm Busse, Jan H. Schönherr, Matthias Diener, Gero Mühl, Jan Richling. “Analyzing Resource Interdependencies in Multi-Core Architectures to Improve Scheduling Decisions.” ACM Symposium on Applied Computing (SAC), 2013. [doi]

  39. Eduardo Roloff, Matthias Diener, Alexandre Carissimi, Philippe O. A. Navaux. “High Performance Computing in the Cloud: Deployment, Performance and Cost Efficiency.” International Conference on Cloud Computing Technology and Science (CloudCom), 2012. [doi]

  40. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux. “Using the Translation Lookaside Buffer to Map Threads in Parallel Applications Based on Shared Memory.” International Parallel & Distributed Processing Symposium (IPDPS), 2012. [doi]

  41. Eduardo Roloff, Francis Birck, Matthias Diener, Alexandre Carissimi, Philippe O. A. Navaux. “Evaluating High Performance Computing on the Windows Azure Platform.” International Conference on Cloud Computing (CLOUD), 2012. [doi]

Books

  1. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux. “Thread and Data Mapping for Multicore Systems.”, 2018. [doi]

Workshops

  1. Matthias Diener, Laxmikant Kale. “Unified data movement for offloading Charm++ applications.” International Workshop on Accelerators and Hybrid Exascale Systems (AsHES), held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS), 2020. [doi]

  2. Eduardo Roloff, Matthias Diener, Emmanuell D. Carreño, Francis B. Moreira, Luciano P. Gaspary, Philippe O. A. Navaux. “Exploiting price and performance tradeoffs in heterogeneous clouds.” International Workshop on Clouds and eScience Applications Management (CloudAM), held in conjunction with the International Conference on Utility and Cloud Computing (UCC), 2017. [doi]

  3. Seonmyeong Bak, Harshitha Menon, Sam White, Matthias Diener, Laxmikant Kale. “Integrating OpenMP into the Charm++ Programming Model.” International Workshop on Extreme Scale Programming Models and Middleware (ESPM2), held in conjunction with SC’17, 2017. [doi]

  4. Matthias Diener, Sam White, Laxmikant V. Kale. “Visualizing, measuring, and tuning Adaptive MPI parameters.” International Workshop on Visual Performance Analysis (VPA), held in conjunction with SC’17, 2017. [doi]

  5. David Beniamine, Matthias Diener, Guillaume Huard, Philippe O. A. Navaux. “TABARNAC: Visualizing and Resolving Memory Access Issues on NUMA Architectures.” Workshop on Visual Performance Analysis (VPA), held in conjunction with SC’15, 2015. [doi]

  6. Rodrigo V. Kassick, Francieli Z. Boito, Matthias Diener, et al. “Trace-based Visualization as a Tool to Understand Applications’ I/O Performance in Multi-Core Machines.” Workshop on Architecture and Multi-Core Applications (WAMCA), 2011. [doi]

  7. Matthias Diener, Felipe L. Madruga, Eduardo R. Rodrigues, et al. “Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors.” International Conference on High Performance Computing and Communications (HPCC), 2010. [doi]

Posters

  1. Douglas Pereira Pasqualin, André Rauber Du Bois, Maurício Lima Pilla, Matthias Diener. “Improving the Performance of Software Transactional Memory Through Sharing-Aware Mapping.” International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2019.

  2. Michael Anderson, Dan Bodony, Alex Brooks, Michael Campbell, Matthias Diener, et al. “Developing Fast Code Through High-Level Annotations.” SIAM Conference on Computational Science and Engineering (CSE), 2017.